1. Field of the Invention
This invention is related to technology used in a semiconductor memory device, especially used in a screening test of a NOR type flash memory and SRAM.
2. Description of the Related Art
During a screening test before shipment of a semiconductor device, what is generally called a READ test is conducted with the purpose of detecting a defective mode which is called a multiple address selection.
Furthermore, as one method of simplifying a test for solving the difficulty of testing on a large scale and complex semiconductor integrated circuit, a Built-In Self Test (referred to below as BIST) control circuit is incorporated into a semiconductor memory device itself as shown in Japanese Laid-Open patent Publication No. 2004-294224 (patent document 1).
However, in testing a NOR type flash memory or an SRAM (Static Random Access Memory) having an automatic sleep function by a tester or BIST control circuit, when the amount of time where an internal address control signal does not change, passes a certain amount of time, the automatic sleep function is activated and the internal address control signal becomes a fixed mode, making the result of the test to the same state as the multiple address selection, which is caused by a defect. Therefore, it is no longer possible to detect a defective mode by the read test.